IMPLEMENTING UPDI FROM SCRATCH
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Part IV — High-Voltage UPDI Activation and Recovery
By the end of Part III, our Arduino Nano could do something genuinely useful.
It could:
- establish ordinary UPDI communications;
- identify an AVR16DU28-I/SP;
- enter NVM programming mode;
- erase Flash;
- write Flash;
- write EEPROM;
- read and write appropriately selected fuses;
- verify programmed contents;
- and coordinate those operations with a Python/PySerial host.
That is already a practical programmer.
But there remains an awkward problem.
What happens if the microcontroller’s UPDI pin is no longer configured as UPDI?
Or, on newer devices, what happens if the application has configured the relevant shared programming function so that ordinary one-wire UPDI activation no longer works?
That is where high-voltage UPDI activation enters the story.
Unfortunately, it is also where a great deal of misinformation appears.
A common statement is:
“UPDI recovery uses 12 volts.”
That statement is sometimes true.
It is also sometimes dangerously wrong.
Microchip currently describes three broad AVR UPDI physical arrangements:
- Older shared UPDI/RESET/GPIO pin — an approximately 12 V pulse can override the alternate pin function.
- Dedicated UPDI pin — UPDI remains available and does not normally need HV recovery.
- Newer shared UPDI/GPIO with separate RESET pin — high voltage is applied to RESET, typically at approximately
VDD + 2 V, not blindly at 12 V.
Our reference devices—the AVR16DU28-I/SP, AVR32DU28-I/SP, and AVR16DD28-I/SP—belong to the newer class of device for which the RESET-side HV activation mechanism is relevant.
That distinction governs nearly everything we are about to build.
210. High Voltage Does Not Program the Flash
Before touching a circuit, repeat the most important concept from Part I:
The high voltage is an activation signal.
It is not the voltage used to write Flash cells.
The sequence is conceptually:
HV pulse
↓
override pin configuration / activate programming path
↓
ordinary UPDI communication
↓
KEY
↓
NVM programming
Once UPDI is active, the communications remain ordinary digital UPDI signaling.
The high-voltage rail is not continuously powering the programming operation.
That is why we will design the HV hardware as a pulse switch, not as a second target supply.
211. Our Reference Devices Use the Modern RESET-HV Method
For the AVR16DU28/AVR32DU28/AVR16DD28-style implementation, Microchip specifies the high-voltage signal on:
RESET
rather than applying 12 V to the UPDI data wire.
The published electrical characteristics for this class specify approximately:
| Parameter | Value |
|---|---|
| Minimum HV level | VDD + 2 V |
| Typical HV level | 7.5 V |
| Maximum HV level | 8.5 V |
| Minimum HV duration | 10 µs |
| Valid-key timeout after HV | about 65 ms |
Microchip explicitly warns that the RESET pin’s absolute maximum rating must never be exceeded.
That means, for a target powered at:
VDD = 5.0 V
the theoretical minimum threshold is approximately:
5.0 V + 2.0 V = 7.0 V
while Microchip’s characterized typical value is:
7.5 V
and the specified ceiling is:
8.5 V
for the applicable devices.
This is a very different electrical problem from 12 V UPDI.
212. What Voltage Should We Set on the Bench Supply?
For our AVR16DU28-I/SP breadboard experiment, with:
VDD ≈ 5.0 V
a sensible bench-supply starting point is:
7.5 V
not 12 V.
Use a current-limited supply.
A conservative laboratory setup might begin with:
HV supply: 7.5 V
current limit: 10–20 mA
because the activation input itself should not require significant current.
The exact current limit is not a Microchip programming specification; it is simply a sensible experimental protection strategy when using a bench supply.
Do not use a current limit so low that wiring capacitance prevents the RESET pulse from reaching the required voltage quickly enough.
213. What About the AVR32DU28-I/SP?
The AVR32DU28 belongs to the same DU family and uses the same broad RESET-HV activation class.
So for our purposes:
AVR16DU28-I/SP
AVR32DU28-I/SP
can use the same bench-HV architecture:
approximately 7.5 V nominal HV
RESET destination
VDD + 2 V minimum threshold
8.5 V maximum characterized HV
subject, as always, to the exact current data sheet revision.
214. What About the AVR16DD28-I/SP?
The AVR16DD28 similarly uses the newer UPDI-v2-style arrangement where a separate RESET signal can participate in high-voltage recovery.
Microchip’s UPDI v2 guidance recommends a four-pin connector containing:
RESET
VCC
GND
UPDI_DATA
specifically because RESET is needed for this class of high-voltage activation.
Therefore our four-wire programming header from Part II was not arbitrary.
It prepares the hardware for this exact operation.
215. The Older 12 V Method Is Still Real
None of this means 12 V UPDI is a myth.
Microchip explicitly identifies older AVR devices—particularly older tinyAVR devices—with a shared:
UPDI / RESET / GPIO
pin.
When that pin has been fused away from UPDI, Microchip’s older high-voltage override method uses approximately:
12 V
on the shared pin.
A documented 12 V enable procedure recommends applying the pulse after power-on reset has been released and holding it for roughly:
100 µs to 1 ms
before tri-stating the programming driver.
That is a separate hardware mode.
We will support it conceptually, but we will not mix its electrical path with our AVR16DU28 example.
216. Never Share One Unlabeled “HV” Output Between Both Methods
A bad programmer front panel would contain:
HV
with no further explanation.
A better design distinguishes:
HV_RESET
from:
HV_UPDI_12V
or at minimum uses firmware-controlled routing plus unmistakable target profiles.
Why?
Because:
7.5 V on RESET
and:
12 V on a shared UPDI pin
are not interchangeable operations.
The wrong one may damage the MCU or surrounding circuitry.
217. A Better Software Representation
Our target descriptor should now contain HV information.
For example:
enum class HvMode : uint8_t
{
None,
ResetLowHv,
SharedPin12V
};
struct HvProfile
{
HvMode mode;
uint16_t nominalMillivolts;
uint16_t minimumMillivolts;
uint16_t maximumMillivolts;
uint32_t minimumPulseUs;
uint32_t typicalPulseUs;
uint32_t keyTimeoutUs;
};
For our AVR16DU28 profile:
constexpr HvProfile AVR16DU28_HV =
{
HvMode::ResetLowHv,
7500,
7000, // assuming 5.0 V target for this experiment
8500,
10,
100,
65000
};
There is a subtle problem with hard-coding:
minimumMillivolts = 7000
because the actual minimum is:
VDD + 2 V
So the mature implementation should compute:
minimumHv =
measuredVtarget + 2000;
rather than storing one fixed number.
That is another reason VTARGET sensing becomes useful.
218. HV Minimum Depends on Target VDD
Suppose the target is running at:
3.3 V
Then the characterized minimum threshold becomes approximately:
3.3 + 2.0 = 5.3 V
You would still remain within the device-specific HV specifications, but blindly applying:
7.5 V
may provide less margin to the absolute maximum than necessary.
This suggests a sophisticated programmer could choose HV dynamically:
measured VDD
↓
compute VDD + margin
↓
clamp to allowed HV range
↓
generate appropriate pulse
Our bench-supply implementation will be manual, but the firmware should still know what voltage it expects.
219. The Bench Supply Is External
We deliberately assume:
External bench supply for HV generation
The Nano does not create the high voltage.
That keeps our circuit simple and makes the experiment easier to inspect.
The architecture is:
BENCH HV SUPPLY
|
|
v
HV SWITCH
|
+———————> target RESET
Arduino Nano
|
+—- HV_ENABLE ——> switch control
The Nano’s job is:
when to connect HV
not:
how to create HV
220. Why We Still Need a Switching Circuit
It might seem tempting to simply touch a wire from the bench supply to RESET.
That can work experimentally.
It is also:
- poorly timed;
- difficult to reproduce;
- easy to slip;
- impossible for firmware to coordinate with the 65 ms key window;
- and hard to automate.
So we want the Nano to switch the externally supplied voltage electronically.
That gives us:
precise timing
repeatability
software interlocks
automated tests
while keeping high-voltage generation outside the programmer.
221. The Basic HV Switch Requirements
Our switch must satisfy several requirements.
When OFF:
target RESET should behave normally
and the HV supply must be electrically isolated from the target.
When ON:
HV rail → RESET
with sufficiently low impedance to reach the desired pulse voltage.
The control input must remain within Nano logic levels.
Therefore:
Nano D7
must never be exposed directly to:
7.5 V
or:
12 V
222. Why a High-Side Switch Is Natural
We want to connect a positive HV rail to RESET.
That is fundamentally a high-side switching problem.
Conceptually:
+7.5 V
|
SWITCH
|
+------ RESET
A P-channel MOSFET is therefore a convenient element.
For example:
+7.5V
|
source
Q1 P-MOSFET
drain
|
+———— RESET
But there is a complication.
To turn a P-channel MOSFET OFF:
gate ≈ source
which means the gate may sit near:
7.5 V
The Nano cannot drive a GPIO to 7.5 V.
Therefore we need another transistor to pull the P-MOSFET gate down.
223. Recommended MOSFET + BJT HV Switch
A very practical hobbyist circuit is:
HV SUPPLY
+7.5 V
|
|
+--------+
|
S Q1
P-MOSFET
D
|
+------ R3 ------> TARGET RESET
|
+--- R1 ---+
100k |
|
Gate Q1
|
+------ Collector Q2
Nano D7 ---- R2 4.7k ---- Base Q2
|
Q2 2N3904
|
Emitter
|
GND
The exact P-channel MOSFET can be something modest whose:
VDS rating
VGS rating
comfortably exceeds our external HV rail.
Because currents are tiny, RDS(on) is not critical.
R1 pulls Q1’s gate to its source:
Q1 OFF
when Q2 is off.
When Nano D7 turns Q2 on:
Q2 pulls Q1 gate toward ground
and Q1 turns on.
224. Add a Gate-Zener if Supporting 12 V
At:
7.5 V
the P-channel MOSFET’s gate-source voltage is usually well within a common ±20 V gate rating.
At:
12 V
it may still be acceptable for many MOSFETs, but a gate clamp is good design practice if the same switch hardware may later see larger rails.
For example:
10 V or 12 V gate-source Zener
depending on device selection.
The exact value must be chosen from the MOSFET’s actual VGS(max) rating.
Do not blindly add a Zener without understanding the desired gate drive.
225. What Is R3?
R3 is an optional series resistor between the switched HV source and target RESET.
For example:
R3 = 470 Ω to 1 kΩ
for initial bench experimentation.
Its purposes are:
- limit accidental current;
- reduce stress during wiring mistakes;
- damp fast edges;
- provide some isolation from attached target circuitry.
But a resistor creates voltage drop.
At the tiny steady-state current expected by the HV-detect input, the drop should be negligible.
If target circuitry loads RESET significantly, the voltage may fall below the required HV threshold.
That itself is useful diagnostic information.
226. Connection Table — MOSFET + BJT HV Switch
| From | Through | To | Purpose |
|---|---|---|---|
| Bench HV + | direct | Q1 P-MOSFET source | HV source |
| Q1 drain | R3, 470 Ω–1 kΩ | target RESET | HV pulse |
| Q1 gate | R1, ~100 kΩ | Q1 source | default OFF |
| Q1 gate | direct | Q2 collector | gate pull-down |
| Nano D7 | R2, ~4.7 kΩ | Q2 base | control |
| Q2 emitter | direct | GND | common reference |
| Bench HV − | direct | GND | common reference |
| Nano GND | direct | target GND | common reference |
For this simple implementation, all grounds are common.
227. Why a BSS138 Alone Is Not the Best High-Side HV Switch
A BSS138 is an N-channel MOSFET.
It is excellent for:
pulling a node LOW
open-drain signaling
gate driving
low-current switching
but we need to connect a positive HV rail to RESET.
Using a single N-channel MOSFET as the high-side switch becomes awkward because the gate must rise above the source voltage to turn it on fully.
That is why:
P-channel MOSFET + NPN
or:
P-channel MOSFET + N-channel MOSFET
is cleaner.
228. MOSFET + MOSFET Alternative
We can replace the 2N3904 with a small N-channel MOSFET:
BSS138
2N7000
2N7002
Conceptually:
Nano D7
|
Gate Q2 N-MOSFET
Q2 drain —- Q1 gate
Q2 source — GND
This eliminates base current.
A typical arrangement:
Nano D7 HIGH
↓
Q2 ON
↓
Q1 gate LOW
↓
Q1 P-MOSFET ON
↓
HV → RESET
This is probably my preferred simple solid-state version.
229. BJT-Only Version
If we want to keep the entire HV switch understandable using common through-hole components, we can also build it from BJTs.
A PNP transistor can provide high-side switching and an NPN transistor can drive it.
Conceptually:
HV
|
Emitter Q1 PNP
Collector
|
+—— RESET
Q1 base
|
resistor
|
Collector Q2 NPN
Nano D7 → resistor → Base Q2
Q2 emitter → GND
This works well at the tiny current required by the HV-detect input.
The transistor voltage ratings still need to exceed the maximum intended HV.
230. Which Circuit Should the Hobbyist Build?
For our article, I recommend three documented options:
Option A — PNP + NPN
Best for:
through-hole construction
breadboards
beginners
Typical devices:
2N3906
2N3904
Option B — P-MOSFET + N-MOSFET
Best for:
very low control current
clean switching
small PCB implementation
Example small N-channel device:
BSS138
2N7000
2N7002
Select the P-channel MOSFET according to voltage and package preference.
Option C — P-MOSFET + 2N3904
A good compromise between:
simple
robust
easy to understand
This is the version we will use in the timing examples.
231. A Manual Safety Jumper Is Worth Adding
A physical jumper can prevent accidental HV application.
For example:
JP1
HV ARM
placed between:
Q1 drain
and:
target RESET
With the jumper removed:
firmware cannot apply HV
even if it contains a bug.
This is a particularly good idea during firmware development.
Software bugs should not automatically become high-voltage events.
232. Add an HV LED Carefully
An optional indicator LED can show:
HV AVAILABLE
or:
HV ACTIVE
But be precise about what it indicates.
A LED connected to the bench HV rail means:
HV supply present
not:
HV being applied to target
An LED driven from the switching control signal can indicate:
HV switch commanded ON
but still does not prove the target actually received the correct voltage.
The most trustworthy confirmation remains:
oscilloscope or ADC measurement
233. Our First HV Test Must Not Include the AVR
Before connecting the target, connect the HV output to:
oscilloscope
and perhaps a benign test resistor.
Then run:
100 µs pulse
and measure:
rise time
peak voltage
pulse width
fall time
off-state leakage
The test circuit is:
Bench HV
|
switch
|
+—— scope probe
|
resistor to ground if desired
Do not connect the AVR until the waveform is known.
234. Recommended Initial Pulse Width
For our modern RESET-HV devices, Microchip specifies:
minimum = 10 µs
for the relevant characterized HV pulse.
A reasonable laboratory starting point is:
100 µs
That is comfortably above the minimum while still being short.
Our firmware:
constexpr uint32_t HV_PULSE_US = 100;
Then:
void hvPulse()
{
digitalWrite(HV_ENABLE_PIN, HIGH);
delayMicroseconds(HV_PULSE_US);
digitalWrite(HV_ENABLE_PIN, LOW);
}
For a production implementation, direct port access or timer control may improve precision.
But unlike 225 kbaud serial bits, a 100 µs pulse has substantial timing margin.
235. Measure the Pulse at RESET, Not at D7
This is essential.
The Nano may produce:
D7 HIGH for 100 µs
while the actual target sees:
6.1 V for 72 µs
because of:
- transistor delay;
- gate charge;
- target loading;
- R3 voltage drop;
- wiring capacitance.
The waveform that matters is:
target RESET relative to target GND.
Always measure there.
236. The 65 ms Key Window
After the HV event, a valid UPDI key must arrive within approximately:
65 ms
on the applicable devices.
That means this is bad:
hvPulse();
Serial.println(“HV pulse complete.”);
delay(100);
sendNvmpKey();
The diagnostic print and 100 ms delay can cause us to miss the activation window.
The sequence should be tightly controlled.
237. The Modern RESET-HV Sequence
For our reference modern devices, the conceptual procedure is:
verify target powered
↓
ordinary reset recommended
↓
apply HV to RESET
↓
remove / tri-state HV
↓
enable ordinary UPDI data path
↓
send SYNCH
↓
send NVMPROG KEY
↓
continue programming entry
Microchip specifically documents sending the NVMPROG key after the first synchronization character following the HV event.
Do not insert unnecessary human-interface work between:
HV
and:
KEY
238. Firmware Should Lock Out Serial Logging During the HV Window
During the HV sequence:
no Serial.print()
until the key has been accepted.
Instead:
struct HvResult
{
bool pulseIssued;
bool keySent;
bool keyAccepted;
uint32_t elapsedUs;
};
Store information in RAM.
Print it afterward.
This keeps debugging output from breaking the protocol it is trying to observe.
239. An HV Activation Function
Conceptually:
UpdiError hvEnterProgramming()
{
if (!hvArmed())
return UpdiError::HvNotArmed;
if (!targetVoltageValid())
return UpdiError::BadTargetVoltage;
// Make sure ordinary UPDI output is released.
updiRelease();
// Apply HV pulse on RESET.
hvSwitchOn();
delayMicroseconds(100);
hvSwitchOff();
// Immediately establish UPDI.
UpdiError err = updiEnable();
if (err != UpdiError::None)
return err;
// Send NVMPROG key within HV timeout.
err = updiSendKey(
UPDI_KEY_NVMPROG,
sizeof(UPDI_KEY_NVMPROG));
if (err != UpdiError::None)
return err;
return verifyNvmpKey();
}
This is still conceptual code.
The exact target-family sequence belongs in an HV backend.
240. Separate HV Backends Too
Just as NVM algorithms vary, so do HV activation algorithms.
A reasonable architecture is:
hv_none.cpp
hv_reset_low.cpp
hv_shared_12v.cpp
Then a device descriptor selects:
HvMode::ResetLowHv
or:
HvMode::SharedPin12V
This prevents a later programmer version from accidentally performing:
shared-pin 12 V method
on:
AVR16DU28
because the function does not even belong to that device profile.
241. Why the RESET Pin Must Be Kept Electrically Clean
Microchip explicitly warns that external circuitry attached to RESET may be damaged when HV is applied and recommends designs that allow such circuitry to be disconnected where necessary.
Imagine:
RESET
|
+—— AVR pin
|
+—— supervisor IC
|
+—— another MCU
|
+—— pushbutton LED circuit
Applying:
7.5 V
to RESET may also apply 7.5 V to those devices.
The AVR may survive.
The reset supervisor might not.
Therefore:
HV compatibility must be considered at the board-design stage.
242. A Series Resistor Does Not Always Solve This
Suppose RESET is connected to another IC through:
1 kΩ
and that IC clamps at:
5.3 V
The clamp may prevent the target RESET node from ever reaching:
7 V
required for HV activation.
A series resistor can reduce current.
It cannot guarantee the correct voltage appears at the target.
Therefore a target designed for HV recovery should ideally provide:
jumper
series isolation
MOSFET isolation
dedicated programming pad
as appropriate.
243. The Recommended Four-Pin UPDI-v2 Header Makes Sense Now
The Microchip UPDI-v2-style connector contains:
1 RESET
2 VCC
3 GND
4 UPDI_DATA
for exactly this reason.
Our Nano programmer should expose the same logical signals.
A suggested hobbyist connector:
| Pin | Signal |
|---|---|
| 1 | RESET/HV |
| 2 | VTARGET |
| 3 | GND |
| 4 | UPDI |
Then:
ordinary programming:
UPDI + VTARGET + GND
HV recovery:
RESET/HV + UPDI + VTARGET + GND
The connector itself does not determine voltage.
Firmware and hardware routing do.
244. Add VTARGET Sensing
Before applying HV, we should know the target voltage.
Our Nano ADC only tolerates voltages within its own allowed input range.
So add a divider.
Suppose we want to tolerate up to:
15 V target sense
while keeping the ADC below:
5 V
A simple divider could use:
Rtop = 22 kΩ
Rbottom = 10 kΩ
Then:
VADC = VTARGET × 10 / (22 + 10)
VADC = VTARGET × 0.3125
At:
VTARGET = 15 V
we get:
VADC ≈ 4.69 V
which remains below 5 V.
245. Add the ADC Series Resistor
Between the divider junction and A0, add:
RADC = 1 kΩ to 4.7 kΩ
For example:
VTARGET
|
[22k]
|
+—- divider node —-[1k]—- A0
|
[10k]
|
GND
The series resistor limits current into the ADC pin during abnormal conditions and works with any clamp/protection scheme we later add.
246. ADC Protection Options
Several hobbyist-friendly options exist.
Schottky clamp to Nano VCC
For example:
A0 —-|<|—- +5 V
using a suitable Schottky diode.
If A0 rises above approximately:
5 V + diode forward voltage
the external diode conducts.
This reduces reliance on the MCU’s internal clamp structures.
TL431/TLV431-based clamp
A shunt reference can create a more deliberate threshold.
This is more complex, but it allows:
defined clamp behavior
rather than a simple diode drop relative to VCC.
Transistor/MOSFET protection
A transistor can disconnect or clamp the ADC input when voltage exceeds a threshold.
That is useful in a sophisticated universal programmer.
For our Nano teaching programmer:
divider
+
series resistor
+
Schottky clamp
is a reasonable balance of simplicity and protection.
247. Connection Table — VTARGET Sense
| From | Through | To |
|---|---|---|
| Target VTARGET | 22 kΩ | divider node |
| Divider node | 10 kΩ | GND |
| Divider node | 1 kΩ | Nano A0 |
| Nano A0 | Schottky clamp | Nano +5 V |
| Nano GND | direct | target GND |
The resistor values are examples, not universal requirements.
Calculate them for the maximum voltage your programmer is intended to encounter.
248. Convert ADC Reading Back to Voltage
With:
Rtop = 22k
Rbottom = 10k
the ratio is:
32 / 10 = 3.2
So:
VTARGET ≈ VADC × 3.2
If the ADC reference is approximately 5.00 V:
float readTargetVoltage()
{
int raw = analogRead(A0);
float vadc =
raw * (5.0f / 1023.0f);
return vadc * 3.2f;
}
For a more accurate tool, measure the Nano’s actual reference voltage or use a calibrated reference.
249. Why VTARGET Sensing Matters for HV
Suppose the device profile says:
HV minimum = VDD + 2 V
and we measure:
VDD = 4.94 V
Then:
minimum HV ≈ 6.94 V
If our bench supply is set to:
6.5 V
the firmware should refuse the operation.
Conversely, if the operator accidentally sets:
9.0 V
for an AVR16DU28 profile with:
maximum = 8.5 V
the firmware should warn and refuse if it can measure the HV rail.
250. Measuring the HV Rail Too
A more capable version can use a second ADC channel:
A1 = HV_SENSE
through another divider.
Then the Nano can verify:
bench supply present?
correct voltage?
before arming the HV switch.
For example:
Target VDD: 5.01 V
HV supply: 7.48 V
HV minimum: 7.01 V
HV maximum: 8.50 V
HV READY
This dramatically reduces operator error.
251. An HV Interlock State Machine
The programmer should not let:
hvSwitchOn()
be called casually.
Use a state machine:
HV_DISABLED
|
v
HV_SUPPLY_DETECTED
|
v
HV_VOLTAGE_VALID
|
v
HV_ARMED
|
v
HV_PULSE
|
v
HV_LOCKED_OUT
After a pulse, return to a safe state unless another explicit sequence is initiated.
252. Physical + Software Interlock Is Better
Best practice for a hobbyist tool is:
physical jumper
+
software target profile
+
voltage measurement
before enabling HV.
All three must agree.
For example:
JP1 inserted? YES
Target profile? AVR16DU28
Measured VTARGET? 5.03 V
Measured HV? 7.47 V
Allowed HV range? 7.03–8.50 V
Destination? RESET
Proceed.
That is far safer than:
digitalWrite(D7, HIGH);
253. The 12 V Shared-Pin Hardware Needs Different Routing
Now consider an older tinyAVR target.
Its HV operation may be:
12 V pulse
↓
shared UPDI/RESET/GPIO pin
That means the same physical node later carries ordinary UPDI data.
We cannot permanently connect our normal Nano D6 interface to that node without ensuring the Nano is protected from 12 V.
This is where isolation becomes absolutely essential.
254. Do Not Depend on the 4.7 kΩ Resistor Alone for 12 V Protection
Suppose:
12 V
appears on the target side of R1:
target UPDI —- 4.7k —- Nano D6
The Nano input protection diode may conduct toward its 5 V rail.
Approximate current:
(12 – 5.3) / 4700
≈ 1.4 mA
That current may seem small.
But deliberately injecting HV into the Nano’s ESD structures is poor design.
It can:
- back-power the 5 V rail;
- disturb the USB interface;
- violate absolute maximum ratings;
- produce unpredictable behavior.
Therefore a proper 12 V-capable programmer should disconnect or clamp the Nano-side data path during the HV pulse.
255. A MOSFET/BJT UPDI Interface Solves More Than Level Shifting
This is where the additional hardware discussed in Part II becomes valuable.
Instead of tying D6 directly to the target through one resistor, we can create a pull-down transmitter:
Nano control
↓
BJT or MOSFET
↓
pull target UPDI LOW
while target-side pull-up behavior establishes HIGH.
Then the Nano itself never has to drive the target line HIGH.
This naturally creates an open-drain-style interface.
A second protected sense path can monitor the target line.
The benefits include:
voltage-domain separation
HV isolation
less bus contention
better multi-voltage support
256. Simple BJT UPDI Transmitter
A basic pull-down stage:
TARGET UPDI
|
+—- Collector Q3 2N3904
|
Nano TX — R4 — Base
|
Emitter
|
GND
When Nano control is HIGH:
Q3 ON
UPDI LOW
When Nano control is LOW:
Q3 OFF
UPDI released
This inverts the control logic.
The firmware can compensate easily.
257. But Receiving Needs a Protected Sense Path
The Nano still needs to read UPDI.
One simple approach is:
TARGET UPDI
|
resistor divider / protection
|
Nano RX sense pin
or a transistor/buffer stage.
A more integrated hobbyist design may use:
BSS138 + 2N3904
with one device handling low-side drive and another providing protected level translation/sensing.
There are several workable topologies.
The correct choice depends on:
target voltage range
HV method
desired baud rate
whether D6 alone must provide TX and RX
For our article, the important architectural point is:
HV-capable hardware should electrically separate the Nano’s 5 V GPIO from the target’s HV-exposed node.
258. Our AVR16DU28 Is Easier Because HV Is on RESET
The modern RESET-HV arrangement is much easier to integrate.
Normal data path:
Nano D6 —- 4.7k —- target UPDI
HV path:
bench HV —- switch —- target RESET
They are separate conductors.
Therefore the Nano UPDI pin never sees the HV pulse at all.
This is another reason the AVR16DU28-I/SP is such a good teaching target.
We can learn HV activation without first solving 12 V isolation on the actual serial data line.
259. Complete Modern-HV Breadboard Architecture
ARDUINO NANO
D6 / PD6 o----[R1 4.7k]--------------------------> TARGET UPDI
D7 o----[R2 4.7k]----> Q2 driver
|
v
Q1 HV switch
|
BENCH +7.5V ------------+
|
+----[R3]-----------------> TARGET RESET
Nano +5V -----------------------------------------> TARGET VDD
Nano GND -----------------------------------------> TARGET GND
Bench HV GND -------------------------------------> TARGET GND
The UPDI data and RESET/HV paths remain distinct.
260. Modern-HV Wiring Table
| Nano / supply | Through | Target | Function |
|---|---|---|---|
| Nano D6 | R1 = 4.7 kΩ | UPDI | ordinary UPDI data |
| Nano D7 | R2 + transistor driver | Q1 | HV switch control |
| Bench HV + | Q1 + optional R3 | RESET | HV pulse |
| Nano +5 V | direct | VDD | target power |
| Nano GND | direct | GND | common ground |
| Bench HV − | direct | GND | common ground |
This is the authoritative connection description.
261. Recommended Bench Test Sequence
Before attempting HV recovery on a real target:
Test 1 — switch off state
Verify:
D7 LOW
RESET ≈ normal reset voltage / VDD
HV absent from target
Test 2 — switch pulse
Command:
100 µs
and verify:
RESET ≈ 7.5 V
pulse width ≈ 100 µs
Test 3 — repeated pulse
Perform:
1000 pulses
without target connected.
Check for:
switch heating
timing drift
stuck-on behavior
Test 4 — voltage interlock
Set bench supply intentionally wrong:
6.0 V
and confirm firmware refuses.
Then:
9.0 V
and confirm it refuses again.
Only after those tests should the AVR be connected.
262. Test Firmware for HV
A minimal serial console command:
hv-test
could produce:
HV TEST
Target: disconnected
HV supply: 7.49 V
Pulse width: 100 us
Pulsing…
DONE
And Python can automate:
1000 pulses
while a scope or frequency counter monitors the output.
This is another example of the test-firmware-as-instrument philosophy from Part II.
263. HV Activation Test on AVR16DU28
Once ordinary UPDI already works, we can deliberately configure the device so that ordinary access requires HV override—but only after preserving a recovery route and confirming the exact fuse behavior from the current data sheet.
Do not make this the first fuse experiment.
The test sequence is:
1. Back up Flash.
2. Back up EEPROM.
3. Back up fuses.
4. Verify ordinary UPDI.
5. Change only the relevant pin configuration.
6. Reset/power-cycle as required.
7. Confirm ordinary UPDI no longer behaves as before.
8. Perform RESET-HV activation.
9. Send NVMPROG key within timeout.
10. Confirm programming mode.
11. Restore safe fuse configuration.
12. Power-cycle.
13. Confirm ordinary UPDI again.
This closes the loop.
264. Why a Power Cycle Matters
Some HV overrides persist until:
POR
rather than being undone by an ordinary soft reset.
Microchip explicitly documents cases where only a Power-on Reset restores the fuse-selected pin function after HV override.
Therefore the programmer should distinguish:
CPU reset
UPDI reset
power cycle
They are not equivalent.
265. Target Power Switching Becomes Very Useful
If the programmer controls target power, it can automate:
power off
wait
power on
wait for POR release
apply HV
send key
instead of relying on the user to manually unplug wires.
A high-side P-MOSFET or load switch can control the target’s 5 V or 3.3 V rail.
For a later version:
Nano D8 = TARGET_POWER_ENABLE
as reserved in Part II.
266. Why Power-Off Is Not Always the Same as RESET
An AVR may retain:
UPDI override state
peripheral state
security state
differently across reset sources.
Therefore firmware should explicitly label actions:
RESET TARGET
POWER CYCLE TARGET
RESET UPDI
instead of presenting one generic:
restart
command.
267. UPDI Disable After HV Programming
For one documented modern HV sequence, Microchip recommends resetting/disabling UPDI after the programming session by writing the UPDI disable bit using STCS.
This tells us that clean session termination should be device-aware.
Our generic:
leaveProgrammingMode();
may eventually need to call:
NVM cleanup
reset
UPDI disable
power-cycle recommendation
depending on the target.
268. The HV Key Must Be Valid
An HV event by itself does not give indefinite programming access.
Microchip’s mechanism requires a valid UPDI activation key inside the timeout window.
This helps prevent accidental high-voltage events such as ESD from leaving the device in programming mode.
So:
HV pulse
without:
valid KEY
should eventually return the device to normal behavior.
That is an intentional safety feature.
269. ESD Is One Reason HV Detection Has a Timeout
A sufficiently large electrostatic transient can look electrically similar to a high-voltage pulse.
Microchip explicitly warns that insufficient external protection can allow ESD to be interpreted as an HV override event.
The key requirement reduces the consequences:
unexpected voltage spike
↓
temporary HV detection
↓
no valid KEY
↓
timeout
↓
normal operation
This is a clever part of the UPDI architecture.
270. The PDID Exception
There is one recovery limitation that deserves special emphasis.
On devices supporting:
PDID — Program and Debug Interface Disable
Microchip warns that once this security feature is activated, high-voltage RESET recovery does not necessarily restore UPDI programming access.
This is not a bricked-device recovery mechanism.
PDID is deliberately intended to prevent external programming/debug access.
Therefore our software must never imply:
“Don’t worry, HV can always recover any fuse setting.”
It cannot.
271. A Safe UI Warning for PDID
A future host utility should say something like:
WARNING
PDID disables external UPDI program/debug access.
High-voltage RESET activation does not restore
external NVM access after PDID is enabled.
Recovery may require an application bootloader,
if one has already been provisioned.
Type:
ENABLE PDID AVR16DU28
to continue.
That is proportional to the consequences.
272. Old-Style 12 V HV Sequence
Now let us briefly describe the older method.
For a compatible older device:
target powered
↓
POR released
↓
apply ~12 V pulse to shared UPDI/RESET pin
↓
hold roughly 100 µs–1 ms
↓
tri-state HV driver
↓
perform required UPDI enable sequence
↓
send valid key
Microchip’s documented 12 V procedure follows this general pattern.
The important word is:
compatible.
Do not infer compatibility from the fact that the MCU “has UPDI.”
273. 12 V Hardware Must Disconnect Normal UPDI Electronics
For this mode, use an actual high-voltage-isolated data architecture.
Conceptually:
+------------- 12 V switch --------+
| |
v |
TARGET UPDI o----------------------------------------+
|
+---- protected sense path ----> Nano
|
+---- transistor pull-down <---- Nano TX
The Nano pin is never directly connected to the 12 V-exposed node.
This is a much more robust architecture than one series resistor.
274. Why the Nano Analyzer Must Also Be Protected
Our Nano UPDI Sniffer/Analyzer from Part II may be connected to the same bus.
If we perform a 12 V HV pulse, the analyzer input must also tolerate or disconnect from that voltage.
Therefore:
Never connect a normal 5 V logic analyzer or Nano input directly to a shared-UPDI node that will receive 12 V.
Use:
divider
buffer
isolation
HV-rated probe
or disconnect the analyzer during the pulse.
The same warning applies to inexpensive USB logic analyzers.
275. The Modern RESET-HV Method Is Analyzer-Friendly
For our AVR16DU28 example:
UPDI data line
never receives the HV pulse.
Therefore the Nano UPDI Sniffer can remain connected to:
UPDI
while a scope channel watches:
RESET/HV
This gives us a beautiful two-channel experiment:
CH1 = RESET/HV
CH2 = UPDI
Then observe:
HV pulse
↓
UPDI SYNCH
↓
KEY bytes
↓
status transaction
in one capture.
276. Suggested Oscilloscope Capture
Configure:
CH1: RESET
CH2: UPDI
Trigger: CH1 rising edge above ~6 V
Then capture perhaps:
10–100 ms window
depending on scope memory.
You should see:
RESET:
_______7.5V_______
_____| |_____
UPDI:
___________________________
\_ SYNCH / KEY / commands
This waveform directly demonstrates what “HV activation” actually means.
277. Analyzer Event Timeline
Our Python/Nano analyzer could eventually produce:
00.000000 ms HV_RESET rising
00.100000 ms HV_RESET falling
00.412000 ms UPDI SYNCH 0x55
00.604000 ms KEY instruction
00.796000 ms KEY byte 0 = 0x20
…
02.140000 ms KEY complete
02.500000 ms ASI_KEY_STATUS read
02.730000 ms NVMPROG accepted
Now we can prove:
key accepted within 65 ms
instead of merely assuming it.
278. Host-Side HV Command
A safe host command might be:
nanoupdi hv-enter
but it should first print:
Target: AVR16DU28
HV mode: RESET low-HV
Target VDD: 5.01 V
HV supply: 7.50 V
Allowed: >7.01 V and <=8.50 V
HV jumper: armed
Proceed? [y/N]
For automated manufacturing, confirmation may be disabled through an explicit machine-mode configuration.
For hobby work, confirmation is appropriate.
279. Separate Manual and Automatic HV Modes
Two useful modes:
Manual bench mode
The user sets:
bench HV voltage
current limit
and firmware controls only the pulse.
Automated supply mode
A future programmer contains:
boost converter
DAC/programmed regulator
HV feedback
and generates the appropriate rail itself.
Our present article uses the first.
The software architecture should not prevent the second.
280. Store the Expected HV in the Device Database
For each device:
HV mode
HV pin
minimum formula
typical voltage
maximum voltage
pulse range
key timeout
should be explicit.
Example conceptual record:
AVR16DU28 = {
“hv_mode”: “reset_low_hv”,
“hv_pin”: “RESET”,
“hv_minimum”: “vdd_plus_2”,
“hv_typical_mv”: 7500,
“hv_max_mv”: 8500,
“hv_min_pulse_us”: 10,
“hv_key_timeout_ms”: 65,
}
Do not store only:
“hv”: true
That is not enough information.
281. Test the Voltage Database Too
Automated tests should verify:
AVR16DU28 → RESET low-HV
AVR32DU28 → RESET low-HV
AVR16DD28 → RESET low-HV
older selected tinyAVR → shared-pin 12 V
dedicated-UPDI devices → no HV required
The test is not about electrical hardware.
It is about preventing a database error from becoming an electrical mistake.
282. HV Should Default to Disabled
On startup:
HV_ENABLE = OFF
TARGET_POWER = safest known state
UPDI released
before:
Serial.begin()
or anything else that might take time.
Use hardware pull resistors so the switches remain OFF during Nano reset.
For example:
D7 → 100k pulldown
if HIGH means “turn HV on.”
That way the HV transistor does not momentarily activate while the ATmega328P pins are inputs during reset.
283. Hardware Default-Off Is Essential
Software eventually runs.
Hardware exists before software runs.
Therefore the switch must be:
OFF
when the Nano is:
unpowered
resetting
bootloading
crashed
A gate/base pull resistor establishes that state independently of firmware.
That is especially important because Nano reset occurs whenever the USB serial port may toggle DTR.
284. Watch the Nano Bootloader
The Nano bootloader briefly owns the MCU before our sketch starts.
Do not assign an HV-enable circuit to a pin that the bootloader may pulse unexpectedly without checking its behavior.
A hardware default-off resistor remains the primary protection.
Then our setup() should immediately establish:
pinMode(HV_ENABLE_PIN, OUTPUT);
digitalWrite(HV_ENABLE_PIN, LOW);
in the appropriate safe polarity.
285. Use Active-Low HV Control if It Makes the Hardware Safer
Depending on the transistor topology, it may be convenient to define:
HIGH = OFF
LOW = ON
or vice versa.
Choose the polarity that gives the safest reset/default behavior.
Then hide it:
void hvSwitchOn();
void hvSwitchOff();
Higher layers should never care whether:
digitalWrite(D7, HIGH)
or:
digitalWrite(D7, LOW)
turns the switch on.
286. A Complete Modern HV Controller Interface
Conceptually:
struct HvStatus
{
float vtarget;
float vhv;
bool jumperArmed;
bool voltageValid;
};
HvStatus hvGetStatus();
UpdiError hvArm();
void hvDisarm();
UpdiError hvPulseReset(
uint32_t pulseUs);
UpdiError hvEnterProgramming();
Only:
hvEnterProgramming()
should orchestrate the entire target-specific sequence.
287. Add a Maximum Pulse Watchdog
Even if firmware requests:
100 µs
a bug might leave the control output active.
A simple software safeguard:
constexpr uint32_t HV_MAX_US = 1000;
But software alone can fail.
A future hardware monostable or one-shot could enforce a hard maximum pulse.
For the simple Nano experiment, an oscilloscope-verified software pulse is adequate, but hardware cutoff is an excellent enhancement for a permanent tool.
288. Why Not Keep HV Applied for Seconds?
Because it serves no useful purpose.
The mechanism is triggered by the pulse.
Continuously holding the pin at HV:
- increases electrical stress;
- increases risk to attached circuitry;
- may interfere with the documented activation sequence;
- provides no programming advantage.
So treat HV like:
trigger pulse
not:
alternate supply voltage
289. Suggested Part-IV Test Firmware Commands
Add:
hv-info
hv-arm
hv-pulse
hv-enter
hv-disarm
power-on
power-off
vtarget
vhv
For example:
NanoUPDI> hv-info
Target: AVR16DU28
HV mode: RESET_LOW
Vtarget: 5.02 V
HV supply: 7.49 V
Required min: 7.02 V
Maximum: 8.50 V
Pulse: 100 us
Key timeout: 65 ms
Armed: NO
That is much safer than hiding the configuration.
290. Python Automated HV Qualification
Our Python/PySerial harness can now automate:
1000 HV pulses
without actually sending programming keys.
Or:
100 complete HV-enter sequences
on a sacrificial target.
Collect:
pulse count
activation success
key acceptance
PROGSTART success
timeouts
target voltage
HV voltage
Then report:
HV activation qualification
Attempts: 1000
HV pulses: 1000
UPDI established: 1000
Key accepted: 1000
PROGSTART: 1000
Failures: 0
This is exactly how we turn a clever circuit into a characterized subsystem.
291. What If the Target Drives RESET?
Normally RESET is an input or dedicated function.
But external circuitry may drive it.
Before applying HV:
ensure no low-impedance external driver is fighting RESET
otherwise:
HV switch → 7.5 V
external driver → 0 V
creates contention.
This is why Microchip recommends circuit-level isolation where necessary.
292. What If RESET Has a Capacitor?
A capacitor from RESET to ground will slow the HV edge.
Suppose:
R3 = 1 kΩ
Creset = 1 µF
The RC constant is:
τ = RC = 1 ms
A:
100 µs
pulse will not allow RESET to reach anywhere near the full HV rail.
That would likely prevent HV activation.
This is another reason excessive reset capacitance is undesirable on modern AVRs.
Measure the actual RESET waveform.
293. What If RESET Has a Pull-Up?
A normal pull-up such as:
10 kΩ to 5 V
is generally much less problematic.
During the HV pulse:
7.5 V
appears through the HV source while the pull-up connects toward 5 V through 10 kΩ.
Approximate current:
(7.5 – 5.0) / 10k
=
0.25 mA
which is modest.
But again, exact acceptability depends on the circuit.
294. Use a Jumper Around Complex Reset Networks
For a development board, an excellent solution is:
RESET MCU —- jumper —- application reset circuit
Remove the jumper during HV programming.
Now the programmer sees:
bare RESET input
instead of an unknown circuit.
This is simple and extremely hobbyist-friendly.
295. The Same Principle Applies to Shared UPDI Pins
For older 12 V devices:
UPDI shared pin —- jumper —- application circuit
can isolate:
LED
sensor
logic input
before 12 V recovery.
A removable jumper is often easier and safer than a complicated protection network.
Microchip itself cites disconnection approaches such as removable jumpers for HV-sensitive attached circuitry.
296. High Voltage and Logic Analyzers
Many inexpensive logic analyzers tolerate only:
3.3 V or 5 V
inputs.
Therefore:
7.5 V RESET
or:
12 V UPDI
may destroy the analyzer.
Use:
oscilloscope probe rated appropriately
for the HV node.
The digital analyzer can remain on the ordinary UPDI line when HV is applied to separate RESET.
297. Safety Is Mostly About Equipment, Not Human Shock
At:
7.5 V
or:
12 V
this is not normally a human electric-shock hazard in the same sense as mains voltage.
The realistic risks are:
damaging the target
damaging the Nano
damaging a USB port
damaging a logic analyzer
damaging attached target circuitry
So the protection strategy is about:
current limiting
voltage limits
isolation
correct routing
interlocks
rather than high-voltage personal protective equipment.
298. Common Ground Is Still Required
Our simple bench-supply switch assumes:
Nano ground
target ground
bench supply negative
are common.
Without a common reference:
7.5 V
at the bench supply has no guaranteed meaning relative to the target RESET threshold.
So connect:
Bench − → target GND → Nano GND
unless you deliberately design galvanic isolation.
299. Beware Earth-Grounded Bench Equipment
Bench supplies and oscilloscopes may have earth-referenced outputs or probe grounds.
Before combining equipment:
check whether supply negative is floating
check whether oscilloscope ground is earth
check whether target USB ground is earth
In a small 5–12 V experiment this is usually straightforward, but unexpected ground paths can still create shorts.
Never clip a grounded oscilloscope probe to a node that is not intended to be earth-referenced.
300. Our Complete HV Development Sequence
The sensible project order is now:
ordinary UPDI
✓
signature reading
✓
NVM programming
✓
Flash verification
✓
EEPROM verification
✓
HV switch breadboard
↓
scope verification
↓
voltage sensing
↓
software interlock
↓
HV pulse without target
↓
HV pulse qualification
↓
sacrificial AVR16DU28 test
↓
restore ordinary UPDI
↓
repeatability testing
This sequence isolates one unknown at a time.
301. Suggested Git Checkpoints
Useful commits:
Add target and HV voltage sensing
Add external RESET-HV switch control
Add HV safety interlocks
Add AVR DU low-HV activation profile
Add automated HV timing tests
Verify AVR16DU28 HV recovery
Add AVR DD HV profile
Document older 12V shared-pin topology
Then tag the successful state:
v0.4.0-hv-updi
before beginning the debugger work.
302. Part IV Review
We can now put the “12 V UPDI” myth into its proper context.
There are multiple UPDI physical arrangements.
For older shared-pin devices:
UPDI / RESET / GPIO
HV recovery may indeed use approximately:
12 V
on the shared pin.
For newer devices with:
UPDI/GPIO
+
separate RESET
the recovery mechanism instead applies a lower high-voltage pulse to:
RESET
with Microchip documenting approximately:
minimum: VDD + 2 V
typical: 7.5 V
maximum: 8.5 V
minimum pulse: 10 µs
key timeout: ~65 ms
for the applicable devices.
Our primary targets:
AVR16DU28-I/SP
AVR32DU28-I/SP
AVR16DD28-I/SP
are treated using this modern RESET-HV architecture.
We therefore designed:
bench HV supply
↓
P-channel high-side switch
↓
target RESET
controlled indirectly by:
Nano D7
through a BJT or N-channel MOSFET.
The Nano never generates the high voltage.
It merely determines when that externally supplied voltage is connected.
We also established that a robust programmer should include:
VTARGET sensing
HV-rail sensing
physical arm jumper
software target profile
voltage-range checking
default-off hardware
pulse-time limits
before allowing HV.
For old 12 V shared-pin targets, we established another critical design requirement:
The normal Nano UPDI electronics must be isolated from the HV-exposed data node.
The classic:
D6 → 4.7 kΩ → UPDI
teaching circuit is not the architecture we should rely on when the same target pin will receive 12 V.
303. What We Can Now Recover
With the appropriate target-specific HV mode, our programmer can potentially recover from situations such as:
UPDI pin configured as GPIO
RESET/UPDI pin function changed by fuse
ordinary one-wire enable no longer available
depending on device architecture.
But it cannot necessarily recover from deliberate security mechanisms such as:
PDID
when those mechanisms are specifically designed to prevent external UPDI programming.
That distinction must remain clear in both the article and our eventual user interface.
304. Where We Go Next
We have now implemented the programming half of the name:
Unified Program and Debug Interface
The remaining major question is:
Can we use our homemade interface as an actual debugger?
The answer is much more interesting than simply “yes.”
UPDI connects to the AVR’s On-Chip Debug system, but a useful debugger requires considerably more machinery than a programmer.
In Part V we will examine:
OCD architecture
debug mode entry
CPU halt
CPU run
reset
program counter
stack pointer
status register
general register access
memory access
I/O register inspection
hardware breakpoints
software breakpoints
single stepping
run-to-address
watch-style memory inspection
debug-session state
We will also distinguish three different things that are frequently confused:
UPDI transport
OCD target protocol
host debugger protocol
because our Nano must eventually sit between:
GDB / IDE
and:
AVR OCD
in much the same way it currently sits between:
Python host
and:
NVMCTRL
We will explore whether:
GDB Remote Serial Protocol
is a practical host-facing interface, what functionality the Nano can reasonably implement, and where a PC-side Python process can shoulder more of the debugger complexity.
We will also use the Nano UPDI Sniffer/Analyzer to study known-good debugger traffic where appropriate.
Finally, after debugging is covered, the last installment will consolidate everything into:
final architecture
complete wiring
recommended hardware variants
programmer/debugger command set
testing strategy
troubleshooting guide
resource directory
project roadmap
final observations
so the series ends not merely with an explanation of UPDI, but with a complete conceptual path from:
one mysterious wire
to:
home-built programmer/debugger platform.